Generally, in a semiconductor memory device such as a dynamic random access memory device, a memory cell is comprised of one access transistor and one storage capacitor. The storage capacitor stores data having a value "1" or "0" therein, which data is transmitted to a bit line through the channel of the access transistor. At that time, the transmission speed of data to the bit line and a voltage level state thereof are defined in dependance upon a voltage level of the word line applied to the gate of the access transistor.
In the meanwhile, the higher the density of a semiconductor memory device, the smaller the size of the transistors, so that an operating power supply voltage is on a descending trend. In case of the high density semiconductor memory device using a low power supply voltage, the voltage level of the word line applied to the gate of the access transistor provided in the memory cell is not high enough to transmit the data stored in the storage capacitor to the bit line, thus reducing an operating speed of the device. In order to solve such a problem, the high density semiconductor memory device includes a word line boosting circuit which serves to raise the voltage level of the word line applied to the gate of the access transistor. The technique on the word line boosting circuit is disclosed in detail in U.S. Pat No. 5,404,330, issued Apr. 4, 1995.
FIG. 1 is a block diagram illustrating a conventional word line boosting method. Referring to FIG. 1, there are provided a word line boosting circuit 5, a row decoder 10 controlled by a row address signal, and a memory cell array block 15 connected to word lines WL0 . . . WLn which are selected by the row decoder 10. As shown in the figure, in a conventional technique, the word line boosting circuit 5 is provided for raising a word line voltage up to a higher voltage than a power supply voltage Vcc, using a charge pumping manner without using a separate power supply voltage Vcc. A word line boosted voltage level is determined in dependence upon a charge sharing ratio between a pumping capacitor (not shown) and a parasitic capacitance of a word line to be enabled. Thereafter, the larger the pumping capacitor as compared with that of the word line parasitic capacitance, the higher the level of the boosted voltage. Hence, the size of the pumping capacitor of the word line boosting circuit 5 causes, with consideration of the loading of the word line, the word line voltage level to be over Vcc+Vtn (where Vtn is a threshold voltage of the access transistor in a memory cell), upon the enablement of the word line. If the size of the pumping capacitor is excessively larger than the loading of the word line, the word line voltage will become too high and the reliability and lifetime of the chip is lessened due to an excessive stress voltage applied thereto. On the other hand, if the size of the pumping capacitor is excessively smaller than the parasitic loading of the word line, a voltage of the bit line is not sufficiently transmitted to the storage capacitor in the memory cell.
FIG. 2 is a block diagram illustrating another conventional word line boosting method of a high density semiconductor memory device. In the figure, two memory cell array blocks 35 and 40 connected to a single word line boosting circuit 5 are selected by row decoders 25 and 30 respectively controlled by the row address signals. FIG. 2 shows that different coding methods of the different row decoders 25 and 30 select the word line upon circuit operation. Upon an active operation, in one of the memory cell array blocks 35 and 40, a constant number of word lines is enabled by the operation of the row decoders 25 and 30, thereby allowing the addressed memory cell array block 35, 40 to be connected to the word line boosting circuit 5. In the other memory cell array block, 35, 40, a constant number of word lines is enabled by the respective row address signal, or no word line enable operation is performed. Accordingly, the word line parasitic loading connected to the word line boosting circuit 5 is changed in accordance with the enablement of one memory cell array block or two memory cell array blocks.
If the word line boosting circuit 5 is designed in consideration of the case where the word line is loaded by two enabled memory cell array blocks 25 and 30, then when only one memory cell array block is enabled, the word line voltage goes to too high and the lifetime and reliability of the memory device are reduced due to an excessive stress voltage applied thereto. On the other hand, if the word line boosting circuit 5 is designed in consideration of the case where, the word line is loaded by enablement of either one of the two memory cell array blocks 25 and 30 then, when the two memory cell array blocks 25 and 30 are enabled, the word line voltage falls to too low a level because the loading of the word line is too much larger than the size of the pumping capacitor of the word line boosting circuit 5.
In one operation cycle of dynamic random access memory as shown in FIGS. 1 and 2, it is apparent to one skilled in the art that the number of enabled word lines is determined by a refresh cycle. In the case of the dynamic random access memory having the same number of word lines, if the number of the refresh cycles is increased, the number of enabled word lines is reduced. If the refresh cycle in one chip is designed to be changed by a specific refresh cycle control signal, the word line loading connected to the word line boosting circuit will be changed in accordance with the refresh cycle control signal. In general, since it is difficult to change the size of the pumping capacitor size stored in the word line boosting circuit, a word line loading compensating circuit should be provided therein.
Typically, in a dynamic random access memory adopting a self refresh, in the case of entering into a self refresh timing, the refresh cycle has to be shortened to the minimum, and the word line loading to be activated within the same refresh time has to be reduced to the minimum, thereby reducing an average operation current consumption. Hence, when the number of the refresh operation cycles is smaller than the number of normal operation cycles, it is necessarily essential that the word line loading compensating circuit be provided.
FIG. 3 is a circuit diagram illustrating a conventional word line loading compensating circuit which compensates for word line loading. That is, this word line loading compensating circuit prevents the word line boosted level from being changed when the word line loading is altered. The circuit includes a pass transistor 45 for receiving a predetermined enable signal .phi.EN, a pull-down transistor 50 whose gate is connected to the channel of the pass transistor 45 and whose one terminal is connected to the output terminal of the word line boosting circuit 5, and a capacitor 55 connected between the other terminal of the pull-down transistor 50 and a ground voltage for storing a moved charge from the output signal of the word line boosting circuit 5. The gate of the pass transistor 45 is connected to a power supply voltage Vcc.
An explanation of the operation of the word line loading compensating circuit of FIG. 3 will be given hereinafter. If the number of word lines connected to the word line boosting circuit 5 is decreased to reduce the word line loading, the enable signal .phi.EN is enabled to a logic "high" state and input to the pass transistor 45. Thereby, the pull-down transistor 50 is turned on and the moved charge from the output signal of the word line boosting circuit 5 is transferred to the capacitor 55. That is, as is seen from the operation mentioned above, if the word line loading is reduced, the pass transistor 45 provides loading to compensate the reduction of the word line loading. In other words, the pass transistor 45 allows the boosted level of the gate of the pull-down transistor 50 being self-boosted, when the word line voltage is boosted, to be fully transferred to the capacitor 55.
However, in the operation of the word line loading compensating circuit, since the boosted voltage level is directly applied to the gate of the pull-down transistor 50, the boosted voltage level is always applied to both ends of the gate oxide layer thereof of the capacitor 55 . As discussed above, the word line boosted voltage level is maintained to be over Vcc+Vtn, considering the threshold voltage Vtn of the access transistor in the memory cell. Hence, an excessive electric field is formed in the gate oxide layer of the capacitor 55 as compared to other capacitors, so that there are problems in that the gate oxide layer is destroyed or caused to be in a bad condition. In the case of the dynamic random access memory device, since the output of the word line boosting circuit is kept at the boosted level during the active cycle, the gate oxide layer of the capacitor receives a voltage causing a continuous stress. Therefore, if the duration of time of the active cycle is lengthened, the application time of the stress voltage to the gate oxide layer of the capacitor is more extended. As a result, an insulation characteristic of the gate oxide layer is broken down due to the application of the stress voltage, and there are problems in that a leakage path is formed in capacitor 55 and the current thereof is leaked to ground. Accordingly, the word line voltage level is lower due to the leaking current and thus the dynamic random access memory device can not perform an accurate operation.